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1/42 preliminary data may 2000 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. m28w320ct m28w320cb 32 mbit (2mb x16, boot block) low voltage flash memory n supply voltage v dd = 2.7v to 3.6v: for program, erase and read v ddq = 1.65v or 2.7v: input/output option v pp = 12v: optional supply voltage for fast program n access time 2.7v to 3.6v: 90ns 2.7v to 3.6v: 100ns n programming time: 10 m s typical double word programming option n program/erase controller (p/e.c.) n common flash interface n memory blocks parameter blocks (top or bottom location) main blocks n block protection unprotection all blocks protected at power up any combination of blocks can be protected wp for block locking n security 64-bit user programmable otp cells 64-bit unique device identifier one parameter block permanently lockable n automatic stand-by mode n program and erase suspend n 100,000 program/erase cycles per block n 20 years of data retention defectivity below 1ppm/year n electronic signature manufacturer code: 20h top device code, m28w320ct: 88bah bottom device code, m28w320cb: 88bbh figure 1. logic diagram ai03521 21 a0-a20 w dq0-dq15 v dd m28w320ct m28w320cb e v ss 16 g rp wp v ddq v pp tsop48 (n) 12 x 20mm m bga47 (gb) 8 x 6 solder balls m bga
m28w320ct, m28w320cb 2/42 figure 2. m bga connections (top view through package) ai02686 c b a 8 7 6 5 4 3 2 1 e d f a4 a7 v pp a8 a11 a13 a0 e dq8 dq5 dq14 a16 v ss dq0 dq9 dq3 dq6 dq15 v ddq dq1 dq10 v dd dq7 v ss dq2 a2 a5 a17 w a10 a14 a1 a3 a6 a9 a12 a15 rp a18 dq4 dq13 g dq12 dq11 wp a19 a20 figure 3. tsop connections dq3 dq9 dq2 a6 dq0 w a3 nc dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15 v dd dq4 dq5 a7 dq7 v pp wp ai03522 m28w320ct m28w320cb 12 1 13 24 25 36 37 48 dq8 a20 a19 a1 a18 a4 a5 dq1 dq11 g a12 a13 a16 a11 v ddq a15 a14 v ss e a0 rp v ss table 1. signal names a0-a20 address inputs dq0-dq7 data input/output, command inputs dq8-dq15 data input/output e chip enable g output enable w write enable rp reset wp write protect v dd supply voltage v ddq power supply for input/output buffers v pp optional supply voltage for fast program & erase v ss ground nc not connected internally
3/42 m28w320ct, m28w320cb description the m28w320c is a 32 mbit non-volatile flash memory that can be erased electrically at the block level and programmed in-system on a word-by- word basis. the device is offered in the tsop48 (10 x 20mm) and the m bga47, 0.75mm ball pitch packages. when shipped, all bits of the m28w320c are in the 1 state. the array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. all blocks are protected against pro- gramming and erase at power up. blocks can be unprotected to make changes in the application and then reprotected. a parameter block osecurity blocko can be permanently protected against pro- gramming and erase in order to increase the data security. each block can be programmed and erased over 100,000 cycles. v ddq allows to drive the i/o pin down to 1.65v. an optional 12v v pp power supply is provided to speed up the program phase at customer production line environment. an internal command interface (c.i.) decodes the instructions to access/modify the memory content. the program/erase controller (p/e.c.) automati- cally executes the algorithms taking care of the timings necessary for program and erase opera- tions. verification is performed too, unburdening the microcontroller, while the status register tracks the status of the operation. the following instructions are executed by the m28w320c: read array, read electronic signa- ture, read status register, clear status register, program, double word program, block erase, program/erase suspend, program/erase re- sume, cfi query, block protect, block lock, block unprotect, protection program. organisation the m28w320c is organised as 2 mbit by 16 bits. a0-a20 are the address lines; dq0-dq15 are the data input/output. memory control is provided by chip enable e, output enable g and write enable w inputs. the program and erase operations are managed automatically by the p/e.c. block pro- tection against program or erase provides addi- tional data security. memory blocks the device features an asymmetrical blocked ar- chitecture. the m28w320c has an array of 71 blocks: 8 parameter blocks of 4 kword and 63 main blocks of 32 kword. m28w320ct has the parameter blocks at the top of the memory ad- dress space while the m28w320cb locates the parameter blocks starting from the bottom. the memory maps are shown in tables 3 and 4. all blocks are protected at power up. instruction are provided to protect, unprotect any block in the application. a second register locks the protection status while wp is low (see block protection de- scription). each block can be erased separately. erase can be suspended in order to perform either read or program in any other block and then re- sumed. program can be suspended to read data in any other block and then resumed. the architecture includes a 128 bits protection register that are divided into two 64-bits segment. in the first one, starting from address 81h to 84h, is written a unique device number, while the sec- ond one, starting from 85h to 88h, is programma- ble by the user. the user programmable segment can be permanently protected programming the bit.1 of the protection lock register (see protec- tion register and security block). the parameter block (# 0) is a security block. it can be permanent- ly protected by the user programming the bit.2 of the protection lock register (see protection regis- ter and security block). table 2. absolute maximum ratings (1) note: 1. except for the rating ooperating temperature rangeo, stresses above those listed in the table oabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. depends on range. symbol parameter value unit t a ambient operating temperature (2) 40 to 85 c t bias temperature under bias 40 to 125 c t stg storage temperature 55 to 155 c v io input or output voltage 0.6 to v ddq +0.6 v v dd ,v ddq supply voltage 0.6 to 4.1 v v pp program voltage 0.6 to 13 v
m28w320ct, m28w320cb 4/42 table 3. top boot block addresses, m28w320ct # size (kword) address range 70 4 1ff000-1fffff 69 4 1fe000-1fefff 68 4 1fd000-1fdfff 67 4 1fc000-1fcfff 66 4 1fb000-1fbfff 65 4 1fa000-1fafff 64 4 1f9000-1f9fff 63 4 1f8000-1f8fff 62 32 1f0000-1f7fff 61 32 1e8000-1effff 60 32 1e0000-1e7fff 59 32 1d8000-1dffff 58 32 1d0000-1d7fff 57 32 1c8000-1cffff 56 32 1c0000-1c7fff 55 32 1b8000-1bffff 54 32 1b0000-1b7fff 53 32 1a8000-1affff 52 32 1a0000-1a7fff 51 32 198000-19ffff 50 32 190000-197fff 49 32 188000-18ffff 48 32 180000-187fff 47 32 178000-17ffff 46 32 170000-177fff 45 32 168000-16ffff 44 32 160000-167fff 43 32 158000-15ffff 42 32 150000-157fff 41 32 148000-14ffff 40 32 140000-147fff 39 32 138000-13ffff 38 32 130000-137fff 37 32 128000-12ffff 36 32 120000-127fff 35 32 118000-11ffff 34 32 110000-117fff 33 32 108000-10ffff 32 32 100000-107fff 31 32 0f8000-0fffff 30 32 0f00000-f7fff 29 32 0e8000-0effff 28 32 0e0000-0e7fff 27 32 0d8000-0dffff 26 32 0d0000-0d7fff 25 32 0c8000-0cffff 24 32 0c0000-0c7fff 23 32 0b8000-0bffff 22 32 0b0000-0b7fff 21 32 0a8000-0affff 20 32 0a0000-0a7fff 19 32 098000-09ffff 18 32 090000-097fff 17 32 088000-08ffff 16 32 080000-087fff 15 32 078000-07ffff 14 32 070000-077fff 13 32 068000-06ffff 12 32 060000-067fff 11 32 058000-05ffff 10 32 050000-057fff 9 32 048000-04ffff 8 32 040000-047fff 7 32 038000-03ffff 6 32 030000-037fff 5 32 028000-02ffff 4 32 020000-027fff 3 32 018000-01ffff 2 32 010000-017fff 1 32 008000-00ffff 0 32 000000-007fff
5/42 m28w320ct, m28w320cb 36 32 0e8000-0effff 35 32 0e0000-0e7fff 34 32 0d8000-0dffff 33 32 0d0000-0d7fff 32 32 0c8000-0cffff 31 32 0c0000-0c7fff 30 32 0b8000-0bffff 29 32 0b0000-0b7fff 28 32 0a8000-0affff 27 32 0a0000-0a7fff 26 32 098000-09ffff 25 32 090000-097fff 24 32 088000-08ffff 23 32 080000-087fff 22 32 078000-07ffff 21 32 070000-077fff 20 32 068000-06ffff 19 32 060000-067fff 18 32 058000-05ffff 17 32 050000-057fff 16 32 048000-04ffff 15 32 040000-047fff 14 32 038000-03ffff 13 32 030000-037fff 12 32 028000-02ffff 11 32 020000-027fff 10 32 018000-01ffff 9 32 010000-017fff 8 32 008000-00ffff 7 4 007000-007fff 6 4 006000-006fff 5 4 005000-005fff 4 4 004000-004fff 3 4 003000-003fff 2 4 002000-002fff 1 4 001000-001fff 0 4 000000-000fff table 4. bottom boot block addresses, m28w320cb # size (kword) address range 70 32 1f8000-1fffff 69 32 1f0000-1f7fff 68 32 1e8000-1effff 67 32 1e0000-1e7fff 66 32 1d8000-1dffff 65 32 1d0000-1d7fff 64 32 1c8000-1cffff 63 32 1c0000-1c7fff 62 32 1b8000-1bffff 61 32 1b0000-1b7fff 60 32 1a8000-1affff 59 32 1a0000-1a7fff 58 32 198000-19ffff 57 32 190000-197fff 56 32 188000-18ffff 55 32 180000-187fff 54 32 178000-17ffff 53 32 170000-177fff 52 32 168000-16ffff 51 32 160000-167fff 50 32 158000-15ffff 49 32 150000-157fff 48 32 148000-14ffff 47 32 140000-147fff 46 32 138000-13ffff 45 32 130000-137fff 44 32 128000-12ffff 43 32 120000-127fff 42 32 118000-11ffff 41 32 110000-117fff 40 32 108000-10ffff 39 32 100000-107fff 38 32 0f8000-0fffff 37 32 0f0000-0f7fff
m28w320ct, m28w320cb 6/42 signal descriptions see figure 1 and table 1. address inputs (a0-a20). the address signals are inputs driven with cmos voltage levels. they are latched during a write operation. data input/output (dq0-dq15). the data in- puts, a word to be programmed or a command to the c.i., are latched on the chip enable e or write enable w rising edge, whichever occurs first. the data output from the memory array, the electronic signature, the block protection status or status register is valid when chip enable e and output enable g are active. the output is high impedance when the chip is deselected, the outputs are dis- abled or rp is tied to v il . commands are issued on dq0-dq7. chip enable (e). the chip enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. e at v ih deselects the memory and reduces the power consumption to the stand-by level. e can also be used to control writing to the command register and to the memo- ry array, while w remains at v il . output enable (g). the output enable controls the data input/output buffers. write enable (w). this input controls writing to the command register, input address and data latches. write protect (wp). this input gives an addition- al hardware protection level against program or erase when pulled at v il , as described in the block protection description. reset input (rp). the rp input provides hard- ware reset of the memory. when rp is at v il ,the memory is in reset mode: the outputs are put to high-z and the current consumption is minimised. when rp is at v ih , the device is in normal opera- tion. exiting reset mode the device enters read ar- ray mode. v dd supply voltage (2.7v to 3.6v). v dd pro- vides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). it ranges from 2.7v to 3.6v. v ddq supply voltage (1.65v to v dd ). v ddq provides the power supply to the i/o pins and en- ables all outputs to be powered independently from v dd .v ddq can be tied to v dd or it can use a separate supply. it can be powered either from 1.65v to v dd . v pp program supply voltage (12v). v pp is both a control input and a power supply pin. the two functions are selected by the voltage range ap- plied to the pin. if v pp is kept in a low voltage range (0v to 3.6v) v pp is seen as a control input. in this case a volt- age lower than v pplk gives an absolute protection against program or erase, while v pp >v pp1 en- ables these functions. v pp value is only sampled at the beginning of a program or erase; a change in its value after the operation has been started does not have any effect and program or erase are carried on regularly. if v pp is used in the range 11.4v to 12.6v acts as a power supply pin. in this condition v pp value must be stable until p/e algorithm is completed (see table 24 and 25). v ss ground. v ss is the reference for all the volt- age measurements.
7/42 m28w320ct, m28w320cb device operations four control pins rule the hardware access to the flash memory: e, g, w, rp. the following opera- tions can be performed using the appropriate bus cycles: read, write the command of an instruc- tion, output disable, stand-by, reset (see table 5). read. read operations are used to output the contents of the memory array, the electronic sig- nature, the status register and the cfi. both chip enable (e) and output enable (g) must be at v il in order to perform the read operation. the chip enable input should be used to enable the device. output enable should be used to gate data onto the output independently of the device selection. the data read depend on the previous command written to the memory (see instructions rd, rsig, rsr, rcfi). read array is the default state of the device when exiting reset or after power-up. write. write operations are used to give com- mands to the memory or to latch input data to be programmed. a write operation is initiated when chip enable e and write enable w are at v il with output enable g at v ih . commands, input data and addresses are latched on the rising edge of w or e, whichever occur first. output disable. the data outputs are high im- pedance when the output enable g is at v ih . stand-by. stand-by disables most of the internal circuitry allowing a substantial reduction of the cur- rent consumption. the memory is in stand-by when chip enable e is at v ih and the device is in read mode. the power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the output enable g or write enable w inputs. if e switches to v ih during program or erase operation, the device en- ters in stand-by when finished. reset. during reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high impedance. the memory is in reset mode when rp is at v il . the power con- sumption is reduced to the stand-by level, inde- pendently from the chip enable e, out-put enable g or write enable w inputs. if rp is pulled to v ss during a program or erase, this operation is abort- ed and the memory content is no longer valid as it has been compromised by the aborted operation. table 5. user bus operations (1) note: 1. x = v il or v ih ,v pph = 12v 5%. table 6. read electronic signature (rsig instruction) operation e g w rp wp v pp dq0-dq15 read v il v il v ih v ih x don't care data output write v il v ih v il v ih x v dd or v pph data input output disable v il v ih v ih v ih x don't care hi-z stand-by v ih xx v ih x don't care hi-z reset x x x v il x don't care hi-z code device e g w a0 a1 a2-a7 a8-a11 a12-a20 dq0-dq7 dq8-dq15 manufact. code v il v il v ih v il v il 0 don't care don't care 20h 00h device code m28w320ct v il v il v ih v ih v il 0 don't care don't care bah 88h m28w320cb v il v il v ih v ih v il 0 don't care don't care bbh 88h
m28w320ct, m28w320cb 8/42 table 7. read block signature (rsig instruction) note: 1. a locked block can be protected odq0 = 1o or unprotected odq0 = 0o; see block protection section. table 8. read protection register and protection register lock (rsig instruction) block status e g w a0 a1 a2-a7 a8-a11 a12-a20 dq0 dq1 dq2-dq15 protected block v il v il v ih v il v ih 0 don't care block address 1 0 00h unprotected block v il v il v ih v il v ih 0 don't care block address 0 0 00h locked block v il v il v ih v il v ih 0 don't care block address x (1) 1 00h word e g w a0-a7 a8-a20 dq0 dq1 dq2 dq3-dq7 dq8-dq15 lock v il v il v ih 80h don't care 0 otp prot. data security prot. data 00h 00h unique id 0 v il v il v ih 81h don't care id data id data id data id data id data unique id 1 v il v il v ih 82h don't care id data id data id data id data id data unique id 2 v il v il v ih 83h don't care id data id data id data id data id data unique id 3 v il v il v ih 84h don't care id data id data id data id data id data otp 0 v il v il v ih 85h don't care otp data otp data otp data otp data otp data otp 1 v il v il v ih 86h don't care otp data otp data otp data otp data otp data otp 2 v il v il v ih 87h don't care otp data otp data otp data otp data otp data otp 3 v il v il v ih 88h don't care otp data otp data otp data otp data otp data
9/42 m28w320ct, m28w320cb instructions and commands sixteen instructions are available (see tables 9 and 10) to perform read memory array, read sta- tus register, read electronic signature, cfi que- ry, erase, program, double word program, clear status register, program/erase suspend, pro- gram/erase resume, block protect, block unpro- tect, block lock and protection register program. status register output may be read at any time, during programming or erase, to monitor the progress of the operation. an internal command interface (c.i.) decodes the instructions while an internal program/erase con- troller (p/e.c.) handles all timing and verifies the correct execution of the program and erase in- structions. p/e.c. provides a status register whose bits indicate operation and exit status of the internal algorithms. the command interface is reset to read array when power is first applied, when exiting from re- set or whenever v dd is lower than v lko . com- mand sequence must be followed exactly. any invalid combination of commands will reset the de- vice to read array. read (rd) the read instruction consists of one write cycle (refer to device operations section) giving the command ffh. next read operations will read the addressed location and output the data. when a device reset occurs, the memory is in read array as default. read status register (rsr) the status register indicates when a program or erase operation is complete and the success or failure of operation itself. issue a read status register instruction (70h) to read the status reg- ister content. the read status register instruction may be issued at any time, also when a program/ erase operation is ongoing. the following read operations output the content of the status regis- ter. the status register is latched on the falling edge of e or g signals, and can be read until e or g returns to v ih . either e or g must be toggled to update the latched data. additionally, any read at- tempt during program or erase operation will auto- matically output the content of the status register. read electronic signature (rsig) the read electronic signature instruction con- sists of one write cycle (refer to device operations section) giving the command 90h. a subsequent read will output the manufacturer code, the de- vice code, the block protection status, or the pro- tection register. see tables 6, 7 and 8 for the valid address. the electronic signature can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of m28w320c. cfi query (rcfi) the common flash interface query mode is en- tered by writing 98h. next read operations will read the cfi data. the cfi data structure contains also a security area; in this section, a 64 bit unique se- curity number is written, starting at this address 81h. this area can be accessed only in read mode and there are no ways of changing the code after it has been written by st. write a read instruction to return to read mode (refer to the common flash interface section). table 9. commands hex code command 00h invalid/reserved 10h alternative program set-up 20h erase set-up 30h double word program set-up 40h program set-up 50h clear status register 70h read status register 90h or 98h read electronic signature, or cfi query b0h program/erase suspend d0h program/erase resume, erase confirm or unprotect confirm ffh read array 01h protect confirm 2fh lock confirm c0h protection program 60h protection set-up
m28w320ct, m28w320cb 10/42 status register bit b7 returns '0' while the erasure is in progress and '1' when it has completed. after completion the status register bit b5 returns '1' if there has been an erase failure. status register bit b1 returns '1' if the user is attempting to pro- gram a protected block. status register bit b3 re- turns a '1' if v pp is below v pplk . erase aborts if rp turns to v il . as data integrity cannot be guaranteed when the erase operation is aborted, the erase must be repeated. a clear sta- tus register instruction must be issued to reset b1, b3, b4 and b5 of the status register. during the execution of the erase by the p/e.c., the memory accepts only the rsr (read status register) and pes (program/erase suspend) instructions. table 10. instructions note: 1. x = don't care. 2. the first cycle of the rd, rsr, rsig or rcfi instruction is followed by read operations in the memory array or special register. any number of read cycle can occur after one command cycle. 3. the signature address recognized are listed in the tables 6, 7 and 8. 4. address 1 and address 2 must be consecutive address differing only for address bit a0. 5. a read cycle after a clsr instruction will output the memory array. mne- monic instruction cycles 1st cycle 2nd cycle 3nd cycle operat. addr. (1) data operat. addr. data operat. addr. data rd read memory array 1+ write x ffh read (2) read address data rsr read status register 1+ write x 70h read (2) x status register rsig read electronic signature 1+ write x 90h or 98h read (2) signature address (3) data rcfi read cfi 1+ write 55h 98h or 90h read (2) cfi address query ee erase 2 write x 20h write block address d0h pg program 2 write x 40h or 10h write address data input dpg (4) double word program 3 write x 30h write address 1 data input write address 2 data input clrs (5) clear status register 1 write x 50h pes program/ erase suspend 1 write x b0h per program/ erase resume 1 write x d0h bp block protect 2 write x 60h write block address 01h bu block unprotect 2 write x 60h write block address d0h bl block lock 2 write x 60h write block address 2fh prp protection register program 2 write x c0h write address data input erase (ee) block erasure sets all the bits within the selected block to '1'. one block at a time can be erased. it is not necessary to program the block with 00h as the p/e.c. will do it automatically before erasing. this instruction uses two write cycles. the first command written is the erase set up command 20h. the second command is the erase confirm command d0h. an address within the block to be erased is given and latched into the memory dur- ing the input of the second command. if the sec- ond command given is not an erase confirm, the status register bits b4 and b5 are set and the in- struction aborts. read operations output the status register after erasure has started.
11/42 m28w320ct, m28w320cb table 11. protection states (1) note: 1. all blocks are protected at power-up, so the default configuration is 001 or 101 according to wp status. 2. current state and next state gives the protection status of a block. the protection status is defined by the write protect pin and by dq1 (= 1 for a locked block) and dq0 (= 1 for a protected block) as read in the read electronic signature instruction with a1 = v ih and a0 = v il . 3. next state is the protection status of a block after a protect or unprotect or lock command has been issued or after wp has changed its logic value. 4. a wp transition to v ih on a locked block will restore the previous dq0 value, giving a 111 or 110. table 12. status register bits note: logic level '1' is high, '0' is low. current state (2) next state after event (3) (wp, dq1, dq0) program/erase allowed protect unprotect lock wp transition 100 yes 101 100 111 000 101 no 101 100 111 001 110 yes 111 110 111 011 111 no 111 110 111 011 000 yes 001 000 011 100 001 no 001 000 011 101 011 no 011 011 011 111 or 110 (4) mnemonic bit name logic level definition note p/ecs 7 p/e.c. status '1' ready indicates the p/e.c. status, check during program or erase, and on completion before checking bits b4 or b5 for program or erase success. '0' busy ess 6 erase suspend status '1' suspended on an erase suspend instruction p/ecs and ess bits are set to '1'. ess bit remains '1' until an erase resume instruction is given. '0' in progress or completed es 5 erase status '1' erase error es bit is set to '1' if p/e.c. has applied the maximum number of erase pulses to the block without achieving an erase verify. '0' erase success ps 4 program status '1' program error ps bit set to '1' if the p/e.c. has failed to program a word. '0' program success vpps 3 v pp status '1' v pp invalid, abort v pps bit is set if the v pp voltage is below v pplk when a program or erase instruction is executed. v pp is sampled only at the beginning of the erase/program operation. '0' v pp ok pss 2 program suspend status '1' suspended on a program suspend instruction p/ecs and pss bits are set to '1'. pss remains '1' until a program resume instruction is given. '0' in progress or completed bps 1 block protection status '1' program/erase on protected block, abort bps bit is set to '1' if a program or erase operation has been attempted on a protected block. '0' no operation to protected blocks 0 reserved
m28w320ct, m28w320cb 12/42 program (pg) the memory array can be programmed word-by- word. this instruction uses two write cycles. the first command written is the program set-up com- mand 40h (or 10h). a second write operation latch- es the address and the data to be written and starts the p/e.c. read operations output the status register con- tent after the programming has started. the status register bit b7 returns '0' while the programming is in progress and '1' when it has completed. after completion the status register bit b4 returns '1' if there has been a program failure. status register bit b1 returns '1' if the user is attempting to pro- gram a protected block. status register bit b3 re- turns a '1' if v pp is below v pplk . programming aborts if rp goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and reprogrammed. a clear status register instruc- tion must be issued to reset b4, b3 and b1 of the status register. during the execution of the program by the p/e.c., the memory accepts only the rsr (read status register) and pes (program/erase suspend) in- structions. double word program (dpg) this feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.the two words must differ only for the address a0. programming should not be attempt- ed when v pp is not at v pph . the operation can also be executed if v pp is below v pph but result could be uncertain. this instruction uses three write cycles. the first command written is the dou- ble word program set-up command 30h. a sec- ond write operation latches the address and the data of the first word to be written, the third write operation latches the address and the data of the second word to be written and starts the p/e.c. read operations output the status register con- tent after the programming has started. the status register bit b7 returns '0' while the programming is in progress and '1' when it has completed. after completion the status register bit b4 returns '1' if there has been a program failure. status register bit b1 returns '1' if the user is attempting to pro- gram a protected block. status register bit b3 re- turns a '1' if v pp is below v pplk . programming aborts if rp goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and reprogrammed. a clear status register instruc- tion must be issued to reset b4, b3 and b1 of the status register. during the execution of the program by the p/e.c., the memory accepts only the rsr (read status register) and pes (program/erase suspend) in- structions. clear status register (clrs) the clear status register uses a single write op- eration which clears bits b1, b3, b4 and b5 to 0. its use is necessary before any new operation when an error has been detected. the clear status register is executed writing the command 50h. program/erase suspend (pes) program/erase suspend is accepted only during the program erase instruction execution. when a program/erase suspend command is written to the c.i., the p/e.c. freezes the program/erase op- eration. program/erase resume (per) continues the program/erase operation. program/erase suspend consists of writing the command b0h without any specific address. the status register bit b2 is set to '1' (within 5 m s) when the program has been suspended. b2 is set to '0' in case the program is completed or in progress. the status register bit b6 is set to '1' (within 30 m s) when the erase has been suspend- ed. b6 is set to '0' in case the erase is completed or in progress. the valid commands while erase is suspended are: program/erase resume, pro- gram, read array, read status register, read identifier, cfi query, block protect, block unpro- tect, block lock and protection program. the user can protect the block being erased issuing the block protect, block lock or protection program commands. in this case the protection status bit will change immediately, but when the erase is re- sumed, the operation will complete the valid com- mands while program is suspended are: program/ erase resume, read array, read status regis- ter, read identifier, cfi query. during program/erase suspend mode, the chip can be placed in a pseudo-stand-by mode by tak- ing e to v ih this reduces active current consump- tion. program/erase is aborted if rp turns to v il . program/erase resume (per) if a program/erase suspend instruction was previ- ously executed, the program/erase operation may be resumed by issuing the command d0h. the status register bit b2/b6 is cleared when program/ erase resumes. read operations output the status register after the program/erase is resumed.
13/42 m28w320ct, m28w320cb the suggested flow charts for programs that use the programming, erasure and program/erase suspend/resume features of the memories are shown from figures 11, 12, 13, 14 and 15. protection register program (prp) the protection register program uses two write cycles. the first command written is the protection program command c0h. the second write opera- tion latches the address and the data to be written to the protection register (see protection register and security block) and start the pe/c. read op- erations output the status register content after the programming has started. the 64 bits user programmable segment (85h to 88h) are pro- grammed 16 bits at a time, it can be protected by the user programming bit 1 of the protection lock register. the bit 1 of the protection lock register protect the bit 2 of the protection lock register. writing the bit 2 of the protection lock register will result in a permanent protection of the security block. attempting to program a previously protect- ed protection register will result in a status regis- ter error (bit 1 and bit 4 of the status register will be set to '1'). the protection of the protection register and/or the security block is not reversible. the protection register program cannot be sus- pended. block protect (bp) the bp instruction use two write cycles. the first command written is the protection setup 60h. the second command is block protect command 01h. the address within the block being protected must be given in order to write the protection state. if the second command is not recognized by the c.i the bit 4 and bit 5 of the status register will be set to in- dicate a wrong sequence of commands. to read the status register write the rsr command. block unprotect (bu) the instruction use two write cycles. the first com- mand written is the protection setup 60h. the sec- ond command is block unprotect command d0h. the address within the block being unprotected must be given in order to write the unprotection state. if the second command is not recognized by the c.i the bit 4 and bit 5 of the status register will be set to indicate a wrong sequence of com- mands. to read the status register write the rsr command. block lock (bl) the instruction use two write cycles. the first com- mand written is the protection setup 60h. the sec- ond command is block lock command 2fh. the address within the block being locked must be given in order to write the locking state. if the sec- ond command is not recognized by the c.i the bit 4 and bit 5 of the status register will be set to indicate a wrong sequence of commands. to read the sta- tus register write the rsr command. table 13. program, erase times and program/erase endurance cycles (t a = 0 to 70 c or 40 to 85 c; v dd = 2.7v to 3.6v) note: t a =25 c. parameter test condition s m28w320c unit min typ (1) max word program v pp =v dd 10 200 m s double word program v pp = 12v 5% 10 200 m s main block program v pp = 12v 5% 0.16 5 sec v pp =v dd 0.32 5 sec parameter block program v pp = 12v 5% 0.02 4 sec v pp =v dd 0.04 4 sec main block erase v pp = 12v 5% 1 10 sec v pp =v dd 110 sec parameter block erase v pp = 12v 5% 0.8 10 sec v pp =v dd 0.8 10 sec program/erase cycles (per block) 100,000 cycles
m28w320ct, m28w320cb 14/42 block protection the m28w320c provide a flexible protection of all the memory providing the protection unprotection and locking of any blocks. all blocks are protected at power-up. each block of the array has two lev- els of protection against program or erase opera- tion. the first level is set by the block protect instruction; a protected block cannot be pro- grammed or erased until a block unprotect in- struction is given for that block. a second level of protection is set by the block lock instruction, and requires the use of the wp pin, according to the following scheme: when wp is at v ih , the lock status is overridden and all blocks can be protected or unprotected; when wp is at v il , lock status is enabled; the locked blocks are protected, regardless of their previous protect state, and protection status cannot be changed. blocks that are not locked can still change their protection status; the lock status is cleared for all blocks at power up. the protection and lock status can be monitored for each block using the read electronic signature (rsig) instruction. protected blocks will output a '1' on dq0 and locked blocks will output a '1' in dq1. protection register and security block the m28w320c features a 128-bit protection reg- ister and a security block in order to increase the protection of a system design. the protection register is divided in two 64-bit segment. the first segment (81h to 84h) is a unique device number, while the second one (85h to 88h) can be pro- grammed by the user. when shipped the user pro- grammable segment is read at '1'. it can be only programmed at '0'; the user programmable segment can be protect- ed writing the bit 1 of the protection lock register (80h). the bit 1 protect also the bit 2 of the protec- tion lock register. the m28w320c feature a se- curity block. the security block is located at 1ff000-1fffff (m28w320ct) or at 000000- 000fff (m28w320cb) of the device. this block can be permanently protected by the user pro- gramming the bit 2 of the protection lock register. the protection register and the protection lock register can be read using the rsig command. a subsequent read in the address starting from 80h to 88h, the user will retrieve respectively the pro- tection lock register, the unique device number segment and the otp user programmable register segment (see table 8). figure 4. security block memory map ai03523 parameter block # 0 user programmable otp unique device number protection register lock 2 1 0 88h 85h 84h 81h 80h
15/42 m28w320ct, m28w320cb power consumption the m28w320c puts itself in one of four different modes depending on the status of the control sig- nals: active power, automatic stand-by, stand-by and reset define decreasing levels of current con- sumption. these allow the memory power to be minimised, in turn decreasing the overall system power consumption. as different recovery time are linked to the different modes, please refer to the ac timing table to design your system. active power when e is at v il and rp is at v ih , the device is in active mode. refer to dc characteristics to get the values of the current supply consumption. automatic stand-by automatic stand-by provides a low power con- sumption state during read mode. following a read operation, after a delay close to the memory access time, the device enters automatic stand- by: the supply current is reduced to icc1 values. the device keeps the last output data stable, till a new location is accessed. stand-by or reset refer to the device operations section. power up the supply voltage v dd and the program supply voltage v pp can be applied in any order. the memory command interface is reset on power up to read memory array, but a negative transition of chip enable e or a change of the addresses is re- quired to ensure valid data outputs. care must be taken to avoid writes to the memory when v dd is above v lko . writes can be inhibited by driving ei- ther e or w to v ih . the memory is disabled if rp is at v il . supply rails normal precautions must be taken for supply volt- age decoupling, each device in a system should have the v dd and v pp rails decoupled with a 0.1 m f capacitor close to the v dd and v pp pins.the pcb trace widths should be sufficient to carry the required v pp program and erase currents.
m28w320ct, m28w320cb 16/42 common flash interface (cfi) the common flash interface (cfi) specification is a jedec approved, standardised data structure that can be read from the flash memory device. cfi allows a system software to query the flash device to determine various electrical and timing parameters, density information and functions supported by the device. cfi allows the system to easily interface to the flash memory, to learn about its features and parameters, enabling the software to configure itself when necessary. tables 14, 15, 16, 17, 18 and 19 show the address used to retrieve each data. the cfi data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. tables 14, 15, 16 and 17 show the addresses used to retrieve each data. the cfi data structure contains also a security area; in this section, a 64 bit unique secu- rity number is written, starting at address 81h. this area can be accessed only in read mode and there are no ways of changing the code after it has been written by st. write a read instruction to return to read mode. refer to the cfi query instruction to understand how the m28w320c enters the cfi query mode. table 14. query structure overview note: the flash memory display the cfi data structure when cfi query command is issued. in this table are listed the main sub-sections detailed in tables 15, 16, 17, 18 and 19. query data are always presented on the lowest order data outputs. table 15. cfi query identification string note: query data are always presented on the lowest - order data outputs (dq7-dq0) only. dq8-dq15 are `0'. offset sub-section name description 00h reserved reserved for algorithm-specific information 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) offset data description 00h 0020h manufacturer code 01h 88bah - top 88bbh - bottom device code 02h-0fh reserved reserved 10h 0051h query unique ascii string oqryo 11h 0052h query unique ascii string oqryo 12h 0059h query unique ascii string oqryo 13h 0003h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 14h 0000h 15h offset = p = 0035h address for primary algorithm extended query table 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported (note: 0000h means none exists) 18h 0000h 19h value = a = 0000h address for alternate algorithm extended query table note: 0000h means none exists 1ah 0000h
17/42 m28w320ct, m28w320cb table 16. cfi query system interface information offset data description 1bh 0027h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 1ch 0036h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 1dh 00b4h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv note: this value must be 0000h if no v pp pin is present 1eh 00c6h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv note: this value must be 0000h if no v pp pin is present 1fh 0004h typical timeout per single byte/word program (multi-byte program count = 1), 2 n m s (if supported; 0000h = not supported) 20h 0000h typical timeout for maximum-size multi-byte program or page write, 2 n m s (if supported; 0000h = not supported) 21h 000ah typical timeout per individual block erase, 2 n ms (if supported; 0000h = not supported) 22h 0000h typical timeout for full chip erase, 2 n ms (if supported; 0000h = not supported) 23h 0004h maximum timeout for byte/word program, 2 n times typical (offset 1fh) (0000h = not supported) 24h 0000h maximum timeout for multi-byte program or page write, 2 n times typical (offset 20h) (0000h = not supported) 25h 0003h maximum timeout per individual block erase, 2 n times typical (offset 21h) (0000h = not supported) 26h 0000h maximum timeout for chip erase, 2 n times typical (offset 22h) (0000h = not supported)
m28w320ct, m28w320cb 18/42 table 17. device geometry definition offset word mode data description 27h 0016h device size = 2 n in number of bytes 28h 0001h flash device interface code description: asynchronous x16 29h 0000h 2ah 0000h maximum number of bytes in multi-byte program or page = 2 n 2bh 0000h 2ch 0002h number of erase block regions within device bit 7 to 0 = x = number of erase block regions note:1. x = 0 means no erase blocking, i.e. the device erases at once in obulk.o 2. x specifies the number of regions within the device containing one or more con- tiguous erase blocks of the same size. for example, a 128kb device (1mb) having blocking of 16kb, 8kb, four 2kb, two 16kb, and one 64kb is consid- ered to have 5 erase block regions. even though two regions both contain 16kb blocks, the fact that they are not contiguous means they are separate erase block regions. 3. by definition, symmetrically block devices have only one blocking region. m28w320ct m28w320ct erase block region information bit 31 to 16 = z, where the erase block(s) within this region are (z) times 256 bytes in size. the value z = 0 is used for 128 byte block size. e.g. for 64kb block size, z = 0100h = 256 => 256 * 256 = 64k bit 15 to 0 = y, where y+1 = number of erase blocks of identical size within the erase block region: e.g. y = d15-d0 = ffffh => y+1 = 64k blocks [maximum number] y = 0 means no blocking (# blocks = y+1 = o1 blocko) note: y = 0 value must be used with number of block regions of one as indicated by (x) = 0 2dh 001eh 2eh 0000h 2fh 0000h 30h 0001h 31h 0007h 32h 0000h 33h 0020h 34h 0000h m28w320cb m28w320cb 2dh 0007h 2eh 0000h 2fh 0020h 30h 0000h 31h 001eh 32h 0000h 33h 0000h 34h 0001h
19/42 m28w320ct, m28w320cb table 18. primary algorithm-specific extended query table table 19. security code area offset data description (p)h = 35h 0050h primary algorithm extended query table unique ascii string aprio 0052h 0049h (p+3)h = 38h 0031h major version number, ascii (p+4)h = 39h 0030h minor version number, ascii (p+5)h = 3ah 0006h extended query table contents for primary algorithm bit 0 chip erase supported (1 = yes, 0 = no) bit 1 erase suspend supported (1 = yes, 0 = no) bit 2 program suspend (1 = yes, 0 = no) bit 3 lock/unlock supported (1 = yes, 0 = no) bit 4 quequed erase supported (1 = yes, 0 = no) bit 31 to 5 reserved; undefined bits are `0' 0000h (p+7)h 0000h (p+8)h 0000h (p+9)h = 3eh 0001h supported functions after suspend read array, read status register and cfi query are always supported during erase or program operation bit 0 program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1 reserved; undefined bits are `0' (p+a)h = 3fh 0000h block lock status defines which bits in the block status register section of the query are implemented. bit 0 block lock status register lock/unlock bit active (1 = yes, 0 = no) bit 1 block lock status register lock-down bit active (1 = yes, 0 = no) bit 15 to 2 reserved for future use; undefined bits are `0' (p+b)h 0000h (p+c)h = 41h 0027h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv (p+d)h = 42h 00c0h v pp supply optimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv (p+e)h 0000h reserved offset data description 80h 00xx protection register lock 81h xxxx 64 bits: unique device number 82h xxxx 83h xxxx 84h xxxx 85h xxxx 64 bits: user programmable otp 86h xxxx 87h xxxx 88h xxxx
m28w320ct, m28w320cb 20/42 table 20. dc characteristics (t a =0to70 c or 40 to 85 c; v dd =v ddq = 2.7v to 3.6v) symbol parameter test conditio n min typ max unit i li input leakage current 0v v in v ddq 1 m a i lo output leakage current 0v v out v ddq 10 m a i cc supply current (read) e=v ss ,g=v ih , f = 5mhz 10 20 ma i cc1 supply current (stand-by or automatic stand-by) e=v ddq 0.2v, rp = v ddq 0.2v 15 50 m a i cc2 supply current (reset) rp = v ss 0.2v 15 50 m a i cc3 supply current (program) program in progress v pp = 12v 5% 10 20 ma program in progress v pp =v dd 10 20 ma i cc4 supply current (erase) erase in progress v pp = 12v 5% 520ma erase in progress v pp =v dd 520ma i cc5 supply current (program/erase suspend) e=v ddq 0.2v, erase suspended 50 m a i pp program current (read or stand-by) v pp >v dd 400 m a i pp1 program current (read or stand-by) v pp v dd 5 m a i pp2 program current (reset) rp = v ss 0.2v 5 m a i pp3 program current (program) program in progress v pp = 12v 5% 10 ma program in progress v pp =v dd 5 m a i pp4 program current (erase) erase in progress v pp = 12v 5% 10 ma erase in progress v pp =v dd 5 m a v il input low voltage 0.5 0.4 v v ddq 2.7v 0.5 0.8 v v ih input high voltage v ddq 0.4 v ddq +0.4 v v ddq 2.7v 0.7 v ddq v ddq +0.4 v v ol output low voltage i ol = 100 m a, v dd =v dd min, v ddq =v ddq min 0.1 v v oh output high voltage i oh = 100 m a, v dd =v dd min, v ddq =v ddq min v ddq 0.1 v v pp1 program voltage (program or erase operations) 1.65 3.6 v v pph program voltage (program or erase operations) 11.4 12.6 v v pplk program voltage (program and erase lock-out) 1v v lko v dd supply voltage (program and erase lock-out) 2v
21/42 m28w320ct, m28w320cb figure 6. ac testing load circuit ai00609b v ddq /2 out c l = 50pf c l includes jig capacitance 3.3k w 1n914 device under test table 21. ac measurement conditions input rise and fall times 10ns input pulse voltages 0tov ddq input and output timing ref. voltages v ddq /2 figure 5. ac testing input output waveform ai00610 v ddq 0v v ddq /2 table 22. capacitance (1) (t a =25 c, f = 1 mhz) note: 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in =0v 6pf c out output capacitance v out =0v 12 pf
m28w320ct, m28w320cb 22/42 table 23. read ac characteristics (1) ( t a = 0 to 70 c or 40 to 85 c) note: 1. see ac testing measurement conditions for timing measurements. 2. sampled only, not 100% tested. 3. g may be delayed by up to t elqv -t glqv after the falling edge of e without increasing t elqv . 4. the device reset is possible but not guaranteed if t plph < 100ns. symbol alt parameter m28w320c unit 90 100 v dd = 2.7v to 3.6v v ddq = 2.7v min v dd = 2.7v to 3.6v v ddq = 1.65v min min max min max t avav t rc address valid to next address valid 90 100 ns t avqv t acc address valid to output valid 90 100 ns t axqx (2) t oh address transition to output transition 0 0 ns t ehqx (2) t oh chip enable high to output transition 0 0 ns t ehqz (2) t hz chip enable high to output hi-z 25 30 ns t elqv (3) t ce chip enable low to output valid 90 100 ns t elqx (2) t lz chip enable low to output transition 0 0 ns t ghqx (2) t oh output enable high to output transition 0 0 ns t ghqz (2) t df output enable high to output hi-z 25 30 ns t glqv (3) t oe output enable low to output valid 30 35 ns t glqx (2) t olz output enable low to output transition 0 0 ns t phqv t pwh reset high to output valid 150 150 ns t plph (2,4) t rp reset pulse width 100 100 ns
23/42 m28w320ct, m28w320cb figure 7. read ac waveforms dq0-dq15 ai02688 valid a0-a20 e rp taxqx tavav valid tavqv telqv telqx tglqv tglqx tphqv power-up and standby address valid and chip enable outputs enabled data valid standby g tghqx tghqz tehqx tehqz note: write enable (w) = high.
m28w320ct, m28w320cb 24/42 table 24. write ac characteristics, write enable controlled (1) (t a = 0 to 70 c or 40 to 85 c) note: 1. see ac testing measurement conditions for timing measurements. 2. sampled only, not 100% tested. 3. the device reset is possible but not guaranteed if t plph < 100ns. 4. the reset will complete within 100ns if rp is asserted while not in program nor in erase mode. 5. applicable if v pp is seen as a logic input (v pp < 3.6v). symbol alt parameter m28w320c unit 90 100 v dd = 2.7v to 3.6v v ddq = 2.7v min v dd = 2.7v to 3.6v v ddq = 1.65v min min max min max t avav t wc write cycle time 90 100 ns t avwh t as address valid to write enable high 50 50 ns t dvwh t ds data valid to write enable high 50 50 ns t elwl t cs chip enable low to write enable low 0 0 ns t phwl t ps reset high to write enable low 90 100 ns t plph (2, 3) t rp reset pulse width 100 100 ns t plrh (2, 4) reset low to program/erase abort 30 30 m s t qvvpl (2, 5) output valid to v pp low 00ns t qvwpl data valid to write protect low 0 0 ns t vphwh (2) t vps v pp high to write enable high 200 200 ns t whax t ah write enable high to address transition 0 0 ns t whdx t dh write enable high to data transition 0 0 ns t wheh t ch write enable high to chip enable high 0 0 ns t whgl write enable high to output enable low 30 30 ns t whwl t wph write enable high to write enable low 30 30 ns t wlwh t wp write enable low to write enable high 50 50 ns t wphwh write protect high to write enable high 50 50 ns t avav t wc write cycle time 90 100 ns t avwh t as address valid to write enable high 50 50 ns
25/42 m28w320ct, m28w320cb figure 8. write ac waveforms, w controlled e g w dq0-dq15 command cmd or data status register rp v pp valid a0-a20 tavav tqvvpl tavwh twhax program or erase telwl twheh twhdx tdvwh twlwh tphwl twhwl tvphwh power-up and set-up command confirm command or data input status register read 1st polling twhqv ai03574 twphwh wp twhgl tqvwpl
m28w320ct, m28w320cb 26/42 table 25. write ac characteristics, chip enable controlled (1) (t a =0to70 c or 40 to 85 c) note: 1. see ac testing measurement conditions for timing measurements. 2. sampled only, not 100% tested. 3. the device reset is possible but not guaranteed if t plph < 100ns. 4. the reset will complete within 100ns if rp is asserted while not in program nor in erase mode. 5. applicable if v pp is seen as a logic input (v pp < 3.6v). symbol alt parameter m28w320c unit 90 100 v dd = 2.7v to 3.6v v ddq = 2.7v min v dd = 2.7v to 3.6v vddq = 1.65v min min max min max t avav t wc write cycle time 90 100 ns t aveh t as address valid to chip enable high 50 50 ns t dveh t ds data valid to chip enable high 50 50 ns t ehax t ah chip enable high to address transition 0 0 ns t ehdx t dh chip enable high to data transition 0 0 ns t ehel t cph chip enable high to chip enable low 30 30 ns t ehgl chip enable high to output enable low 30 30 ns t ehwh t wh chip enable high to write enable high 0 0 ns t eleh t cp chip enable low to chip enable high 50 50 ns t phel t ps reset high to chip enable low 90 100 ns t plph (2, 3) t rp reset pulse width 100 100 ns t plrh (2, 4) reset low to program/erase abort 30 30 m s t qvvpl (2, 5) output valid to v pp low 0 0 ns t qvwpl data valid to write protect low 0 0 ns t vpheh (2) t vps v pp high to chip enable high 200 200 ns t wlel t cs write enable low to chip enable low 0 0 ns t wpheh write protect high to chip enable high 50 50 ns t avav t wc write cycle time 90 100 ns t aveh t as address valid to chip enable high 50 50 ns
27/42 m28w320ct, m28w320cb figure 9. write ac waveforms, e controlled e g dq0-dq15 command cmd or data status register rp v pp valid a0-a20 tavav tqvvpl taveh tehax program or erase twlel tehwh tehdx tdveh teleh tphel tehel tvpheh power-up and set-up command confirm command or data input status register read 1st polling tehqv ai03575 w twpheh wp tehgl tqvwpl
m28w320ct, m28w320cb 28/42 figure 10. reset ac waveform ai03537 tphqv rp tplph rp tplph reset during read mode reset during program with t plph t plrh tplrh tphwl tphel abort complete rp tplph reset during program/erase with t plph >t plrh tplrh tphwl tphel abort complete reset
29/42 m28w320ct, m28w320cb figure 11. program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared (clrs instruction) before further p/e.c. operations. write 40h or 10h command ai03538 start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) program instruction: write 40h or 10h command write address & data (memory enters read status state after the program instruction) do: read status register (e or g must be toggled) if pes instruction given execute suspend program loop while b7 = 1 if b3 = 1, v pp invalid error: error handler if b4 = 1, program error: error handler yes end yes no b1 = 0 program to protected block error (1, 2) if b1 = 1, program to protected block error: error handler suspend suspend loop no yes
m28w320ct, m28w320cb 30/42 figure 12. double word program flowchart and pseudo code note: 1. status check of b1 (protected block), b3 (v pp invalid) and b4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared (clrs instruction) before further p/e.c. operations. 3. address 1 and address 2 must be consecutive addresses differing only for address bit a0. write 30h command ai03539 start write address 1 & data 1 (3) read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1, 2) program error (1, 2) dpg instruction: write 30h command write address 1 & data 1 (3) write address 2 & data 2 (3) (memory enters read status state after the program instruction) do: read status register (e or g must be toggled) if pes instruction given execute dpg suspend loop while b7 = 1 if b3 = 1, v pp invalid error: error handler if b4 = 1, program error: error handler yes end yes no b1 = 0 program to protected block error (1, 2) if b1 = 1, program to protected block error: error handler suspend suspend loop no yes write address 2 & data 2 (3)
31/42 m28w320ct, m28w320cb figure 13. program suspend & resume flowchart and pseudo code write 70h command ai03540 read status register yes no b7=1 yes no b2=1 program continues write a read command pes instruction: write b0h command do: read status register (e or g must be toggled) while b7 = 1 if b2 = 0 program completed write d0h command per instruction: write d0h command to resume the program if the program operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend was not issued). read data from another address start write b0h command program complete write ffh command read data
m28w320ct, m28w320cb 32/42 figure 14. erase flowchart and pseudo code note: 1. if an error is found, the status register must be cleared (clrs instruction) before further p/e.c. operations. write 20h command ai03541 start write block address & d0h command read status register yes no b7 = 1 yes no b3 = 0 no b4, b5 = 0 v pp invalid error (1) command sequence error (1) ee instruction: write 20h command write block address (a12-a20) & command d0h (memory enters read status state after the ee instruction) do: read status register (e or g must be toggled) if pes instruction given execute suspend erase loop while b7 = 1 if b3 = 1, v pp invalid error: error handler if b4, b5 = 1, command sequence error: error handler yes no b5 = 0 erase error (1) yes no suspend suspend loop if b5 = 1, erase error: error handler end yes no b1 = 0 erase to protected block error (1) if b1 = 1, erase to protected block error: error handler yes
33/42 m28w320ct, m28w320cb figure 15. erase suspend & resume flowchart and pseudo code write 70h command ai03542 read status register yes no b7=1 yes no b6=1 erase continues pes instruction: write b0h command do: read status register (e or g must be toggled) while b7 = 1 if b6 = 0, erase completed write d0h command read data from another block or program/protection program or block protect/unprotect/lock start write b0h command erase complete write ffh command read data per instruction: write d0h command to resume erasure if the erase operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend was not issued).
m28w320ct, m28w320cb 34/42 figure 16. command interface and program erase controller flowchart (a) note: 1. if no command is written, the command interface remains in its previous valid state. upon power-up, on exit from power-down or if v dd falls below v lko , the command interface defaults to read array mode. 2. p/e.c. status (ready or busy) is read on status register bit 7. ai03543 read signature yes no 90h read status yes 70h no clear status yes 50h no program set-up yes 40h or 10h no erase set-up yes 20h no erase command error yes ffh wait for command write (1) read status read array yes d0h no a b no c cfi query yes 98h no yes 60h no bp/bu/bl set-up prp set-up yes c0h no dpg set-up yes 30h no c d 01h d0h 2fh prp ready (2) b no no no no bp/bu/bl command error block protect block unprotect block lock yes yes yes yes
35/42 m28w320ct, m28w320cb figure 17. command interface and program erase controller flowchart (b) note: 2. p/e. c. status (ready or busy) is read on status register bit 7. read status yes no 70h b erase yes ready (2) no a b0h no read status yes ready (2) no erase suspend yes d0h read array yes erase suspended read status (read status) yes no (read status) no erase resume 90h no read signature yes 98h no cfi query yes 40h or 10h no program set-up yes c no 30h dpg set-up yes c no 60h bp/bu/bl set-up yes d no c0h prp set-up prp ready (2) yes yes b no ai03544
m28w320ct, m28w320cb 36/42 figure 18. command interface and program erase controller flowchart (c) note: 2. p/e. c. status (ready or busy) is read on status register bit 7. read status yes no 70h b program yes ready (2) no c b0h no read status yes ready (2) no program suspend yes d0h read array yes program suspended read status (read status) yes no (read status) no program resume 90h no read signature yes 98h no cfi query yes ai03545
37/42 m28w320ct, m28w320cb table 26. ordering information scheme devices are shipped from the factory with the memory content bits erased to '1'. table 27. daisy chain ordering scheme for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the stmicroelectronics sales office nearest to you. example: m28w320ct 90 n 6 t device type m28 operating voltage w=v dd = 2.7v to 3.6v; v ddq = 1.65v or 2.7v device function 320c = 32 mbit (2 mb x16), boot block array matrix t = top boot b = bottom boot random speed 90 = 90 ns 100 = 100 ns package n = tsop48: 12 x 20 mm gb = m bga47: 0.75 mm pitch temperature range 1=0to70 c 6=40to85 c optio n t = tape & reel packing example: m28w320c -gb t device type m28w320c daisy chain -gb = m bga47: 0.75 mm pitch optio n t = tape & reel packing
m28w320ct, m28w320cb 38/42 table 28. revision history date revision details february 2000 first issue 04/19/00 daisy chain part numbering defined m bga package outline diagram change (figure 20) m bga chain diagrams, package and pcb connection re-designed (figure 21, 22) 05/17/00 m bga package outline diagram and package mechanical data change (figure 20, table 30)
39/42 m28w320ct, m28w320cb table 29. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data symbol mm inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.17 0.27 0.0067 0.0106 c 0.10 0.21 0.0039 0.0083 d 19.80 20.20 0.7795 0.7953 d1 18.30 18.50 0.7205 0.7283 e 11.90 12.10 0.4685 0.4764 e 0.50 0.0197 l 0.50 0.70 0.0197 0.0276 a 0 5 0 5 n48 48 cp 0.10 0.0039 figure 19. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline drawing is not to scale. tsop-a d1 e 1n cp b e a2 a n/2 d die c l a1 a
m28w320ct, m28w320cb 40/42 table 30. m bga47 - 8 x 6 balls, 0.75 mm pitch, package mechanical data symbol mm inch typ min max typ min max a 1.000 0.0394 a1 0.180 0.0071 a2 0.700 0.0276 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 d 10.500 10.450 10.550 0.4134 0.4114 0.4154 d1 3.750 0.1476 ddd 0.080 0.0031 e 0.750 0.0295 e 6.390 6.340 6.440 0.2516 0.2496 0.2535 e1 5.250 0.2067 fd 3.375 0.1329 fe 0.570 0.0224 figure 20. m bga47 - 8 x 6 balls, 0.75 mm pitch, bottom view package outline drawing is not to scale. d1 d e1 e a2 a1 a bga-g06 ddd e e se sd b fd fe ball oa1o
41/42 m28w320ct, m28w320cb figure 21. m bga47 daisy chain - package connections (top view through package) figure 22. m bga47 daisy chain - pcb connections (top view through package) ai03295 c b a 8 7 6 5 4 3 2 1 e d f ai3296 c b a 8 7 6 5 4 3 2 1 e d f start point end point
m28w320ct, m28w320cb 42/42 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics ? 2000 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a . http://w ww.st.com

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